Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
In keeping with Moore's Law, the number of transistors that can be practicably incorporated into an integrated circuit has doubled approximately every two years. This trend has continued for more than half a century and is expected to continue until at least 2015 or 2020. However, simply adding more transistors to a single-threaded processor no longer produces a significantly faster processor. Instead, increased system performance has been attained by integrating multiple processor cores on a single chip to create a chip multiprocessor, and sharing processes between the multiple processor cores of the chip multiprocessor. Such processors can greatly reduce processing time for applications that have high levels of concurrency, such as applications in which multiple computations can be executed simultaneously or in parallel with each other.
In practice, efficient use of all processor cores in high core-count chip multiprocessors is difficult, since threshold voltage can no longer be scaled down without exponentially increasing the static power consumption incurred due to leakage current in the chip multiprocessor. As a result, the power budget available per core in high core-count chip multiprocessors is projected to decrease in each future technology generation. This situation results in a phenomenon referred to as the “power wall,” “utility wall,” or “dark silicon,” where an increasing fraction of a high core-count chip multiprocessor may not be powered at full frequency or powered on at all. Thus, performance improvements in such chip multiprocessors may be strongly contingent on energy efficiency of a multiprocessor.